Prompted by the development of new types of sophisticated Field Programmable Devices (FPDs), the process of designing digital hardware has changed dramatically over the past few years. Unlike previous generations of technology, in which board level designs included large numbers of Small Scale Integration (SSI) chips containing basic gates, virtually every digital design that is produced today consists substantially of high density devices. High density devices are not only used for custom devices like processors and memory, but also for logic circuits such as Finite State Machines (FSM), counters, registers, and decoders.
High density gate arrays have been used to implement FPD functions when targeted for high volume systems, however, gate array Non-Recoverable Engineering (NRE) expenses and development schedules often preclude their use in prototyping, or other low volume implementations. For these reasons, most prototypes, as well as an increasing number of production designs, are now implemented with FPDs. Some of the most compelling advantages realized when using FPDs are: instant manufacturing turnaround; low startup costs; low financial risk; and ease of design change. Design changes are easily implemented by the end user through the use of Computer Aided Design (CAD) tools, which include software for the following exemplary tasks: initial design entry; logic optimization; device fitting; simulation; and configuration.
Clock division, for example, is a common function that is often programmed by the end user of an FPD. Clock division can also involve the use of a dedicated, programmable clock divider, to perform fixed divide-by ratios between (for example, ÷2 and ÷16), to generate a finite set of clock rates. In an FPD, the user programmable logic portion of the FPD may be utilized by the end user for clock division. The user programmable logic portion of an FPD may be implemented, for example, through the use of: the Configurable Logic Blocks (CLB) and Input/Output (I/O) blocks in Field Programmable Gate Arrays (FPGA); or by the Product Term Array (PTA) and macrocell arrangement of the Complex Programmable Logic Device (CPLD). If the user requires divide-by ratios in excess of the finite set of clock rates, for example, the complexity of the programmable logic increases dramatically.
Historically, dedicated clock dividers have primarily been provided on FPGAs. Consequently, the CPLD user wishing to implement clock division is faced with a dilemma: either use a portion of the available macrocells on the CPLD to implement the clock divider, or change over to an FPGA to realize his particular design. In many instances, however, use of the FPGA is cost prohibitive, whereas utilizing macrocells within a CPLD is an inefficient use of user programmable logic. Today's logic designer is in need of additional design solutions that provides both efficient use of hardware resources, while allowing adequate cost control.
Accordingly, there is a need in the programmable logic device industry to provide the circuit designer with such options not currently offered in FPD designs.
An apparatus and method that addresses the aforementioned problems, as well as other related problems, are therefore desirable.